发明名称 Silicide formation due to improved SiGe faceting
摘要 An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.
申请公布号 US9202883(B2) 申请公布日期 2015.12.01
申请号 US201514744384 申请日期 2015.06.19
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Ekbote Shashank S.;Lim Kwan-Yong;Eshun Ebenezer;Choi Youn Sung
分类号 H01L29/08;H01L29/45;H01L29/161;H01L27/088;H01L27/02;H01L21/336 主分类号 H01L29/08
代理机构 代理人 Garner Jacqueline J.;Cimino Frank D.
主权项 1. An integrated circuit, comprising: a substrate comprising semiconductor material extending to a top surface of said substrate; field oxide disposed in said substrate; a first gate structure over said semiconductor material proximate to said field oxide, said first gate structure comprising: a gate dielectric layer over said semiconductor material; anda gate on said gate dielectric layer of said first gate structure; a second gate structure over said field oxide, said second gate structure comprising a gate on said gate dielectric layer of said second gate structure, such that said gate of said second gate structure does not overlap a sidewall of said field oxide facing the first gate structure; a silicon-germanium source/drain region in said substrate between said first gate structure and said second gate structure, such that a top edge of a boundary between said silicon-germanium source/drain region and said field oxide does not extend more than one third of a depth of said silicon-germanium source/drain region from a top surface of said semiconductor material; dielectric spacers adjacent to lateral surfaces of said gate of said second gate structure, extending onto said silicon-germanium source/drain region; metal silicide on said silicon-germanium source/drain region; and a contact between said first gate structure and said second gate structure, such that at least half of a bottom of said contact directly contacts said metal silicide on said silicon-germanium source/drain region.
地址 Dallas TX US