发明名称 Cascode circuit integration of group III-N and group IV devices
摘要 In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can be situated over the group IV transistor die.
申请公布号 US9202811(B2) 申请公布日期 2015.12.01
申请号 US201314073783 申请日期 2013.11.06
申请人 Infineon Technologies Americas Corp. 发明人 Briere Michael A.
分类号 H01L25/10;H01L27/088;H01L25/18;H01L21/8258 主分类号 H01L25/10
代理机构 Farjami & Farjami LLP 代理人 Farjami & Farjami LLP
主权项 1. An integrated assembly comprising: a printed circuit board; a depletion mode III-Nitride transistor die and a group IV transistor die coupled to said printed circuit board; said depletion mode HI-Nitride transistor die situated on one side of said printed circuit board and said group IV transistor die situated on an opposing side of said printed circuit board; at least one via in said printed circuit board electrically connecting said depletion mode III-Nitride transistor die to said group IV transistor die; wherein said group IV transistor die is configured to receive a gate drive signal through a trace situated on said one side of said printed circuit board.
地址 El Segundo CA US