Integrated circuit floorplan having feedthrough buffers

摘要

A method and a system are provided for planning feedthrough ports on a floorplan for an integrated circuit. In one example, the system groups paths (e.g., nets) into mutually exclusive families of paths (e.g., nets). The system analyzes the simpler path combinations for each path family. Advantageously, the system can find consistent design solutions for paths (e.g., nets), while adding fewer ports and fewer nets, within a practical amount of time.

主权项

1. A method of generating design data for an integrated circuit, the method comprising:
identifying one or more driver-sink pairs on instantiations of modules, wherein the modules include a driver module, an intermediate module, and a sink module; for a first set of instantiations, generating a first path that extends from a driver instantiation (A1), across an intermediate instantiation (B1), to a sink instantiation (C1); for a second set of instantiations, generating a second path that extends from the driver instantiation (A2), across the intermediate instantiation (B2), to the sink instantiation (C2); and determining that the first path and the second path cross at an identical input location on the intermediate instantiations; in response to the identical input location, generating a first input port on the intermediate module, wherein the first input port on the intermediate module is assigned a first family identifier and a first input port location, the first input port and the first input port location defining design data; and generating a photomask for the integrated circuit from the design data.