Processor and data processing method incorporating an instruction pipeline with conditional branch direction prediction for fast access to branch target instructions

摘要

Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.

主权项

1. A processor comprising:
a branch instruction history table (BHT) storing initial direction predictions for conditional branch instructions stored in an instruction cache, each direction prediction being one of taken and not taken; a branch instruction target address cache (BTAC) storing, for any conditional branch instructions previously predicted as taken, target addresses and override bits, said branch instruction history table (BHT) and said branch instruction target address cache (BTAC) each being indexed by instruction cache addresses; an instruction fetch address register essentially simultaneously submitting a specific address for a specific instruction in said instruction cache to said instruction cache, said branch instruction history table (BHT) and said branch instruction target address cache (BTAC) such that reading of said branch instruction history table (BHT), said branch instruction target address cache (BTAC) and said instruction cache occurs in parallel during a same clock cycle,
said branch instruction history table (BHT) outputting, in response to said specific address, a first signal indicative of an initial direction prediction stored in said branch instruction history table (BHT) for said specific instruction, andsaid branch instruction target address cache (BTAC) outputting, in response to said specific address, a second signal indicative of whether said specific instruction is entered in said branch instruction target address cache (BTAC) and a third signal indicative of an override bit associated with said specific instruction; and a direction predictor in communication with said branch instruction history table (BHT) and said branch instruction target address cache (BTAC), said direction predictor performing the following:
receiving said first signal, said second signal, and said third signal;using combinational logic to perform a comparison of said second signal and said third signal; anddepending upon results of said comparison, selecting one of said first signal and said second signal to control a determination of a final direction prediction for said specific instruction.