发明名称 Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation
摘要 A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.
申请公布号 US9202533(B2) 申请公布日期 2015.12.01
申请号 US201414156613 申请日期 2014.01.16
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Tabata Hideyuki;Tsukamoto Takayuki
分类号 G11C7/10;G11C29/34;G11C13/00;G11C29/02;G11C29/52 主分类号 G11C7/10
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A nonvolatile semiconductor memory device comprising: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein, where the number of the bays selected simultaneously is the number of simultaneously selected bays, and the number of the memory cells selected simultaneously in one of the bays is the number of simultaneously selected bits, the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.
地址 Minato-ku JP