Method of generating test patterns for detecting small delay defects

摘要

A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.

主权项

1. A method of generating test patterns for testing an integrated circuit (IC) for small delay defects (SDDs), the method comprising:
providing static timing data for interconnect paths that link sequential elements of the IC, the static timing data including interconnect delay values of the interconnect paths, set-up and clock to Q delays of sequential elements of the paths, and latencies of associated clock networks; modifying the interconnect delay values of the interconnect paths by introducing values corresponding to set-up and clock to Q delays of the sequential elements of the paths and to latencies of the associated clock networks; and selecting critical nodes to target and generating test patterns targeting the selected critical nodes using timing slack resulting from the modified interconnect delays.