Nanoscale silicon Schottky diode array for low power phase change memory application

摘要

Methods and devices associated with a phase change memory include Schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an N+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the N+ buried layer, and forming deep trench isolations through the epitaxial layer and the N+ buried layer along a first direction. The method also includes forming shallow trench isolations in the diode array region and in the peripheral region along a second line direction. The method also includes forming an N− doped region between the deep and shallow trench isolations and forming a metal silicide on a surface of the N− doped region.

主权项

1. A method of manufacturing a semiconductor device having a plurality of Schottky diodes, the method comprising:
providing a P-type semiconductor substrate; defining a diode array region having the plurality of Schottky diodes and a peripheral device region on the P-type semiconductor substrate; forming an N+ buried layer in the diode array region; forming a semiconductor epitaxial layer on a portion of the peripheral device region and on the N+ buried layer; forming a plurality of deep trench isolations through at least the epitaxial layer and the N+ buried layer along a first direction; forming a plurality of shallow trench isolations within the diode array region and within the peripheral device region along a second direction, the shallow trench isolations having a depth equal to or greater than a thickness of the epitaxial layer; wherein forming a plurality of shallow trench isolations comprises:
forming a plurality of shallow trenches within the epitaxial layer of the diode array region and within the epitaxial layer of the peripheral device region;forming a liner layer overlying the shallow trenches;performing an ion implantation into the liner layer to form a P+ protection layer;subjecting the P+ protection layer to an annealing treatment;filling the shallow trenches with an insulation material; andplanarizing the insulation material using a chemical mechanical polishing process; wherein performing an ion implantation comprises implanting dopants at an energy in a range between 5 KeV and 40 KeV, a dose in a range between 1.0×1012 to 4.0×1015 atoms per cm2, and an implant angle in a range of 45 degrees and 70degrees relative to a surface of the semiconductor substrate, the dopants comprising boron, boron fluoride, or indium; forming an N− doped region within a region of the epitaxial layer disposed between the deep trench isolations and the shallow trench isolations of the diode array region; and forming a metal silicide on the N− doped region.