System and method of matching data rates

摘要

The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus. The logic may be adapted to receive data and select the first memory or the second memory to store data.

主权项

1. A device comprising:
a bridge chip including:
a first chip select output directly connected to a first memory to selectively enable the first memory to store data received from a first data bus;a second chip select output directly connected to a second memory to selectively enable the second memory to store data via a second data bus;memory selection logic configured to selectively enable the first memory and the second memory to store data;an output coupled to a second data bus directly connected to the second memory; a data storage controller directly connected to the bridge chip and directly connected to the first memory via the first data bus, through which the data storage controller stores data in the first memory when the memory selection logic selectively enables the first memory, and the data storage controller is indirectly coupled to the second memory via the bridge chip; and wherein the bridge chip receives data from the data storage controller via a third data bus and passes received data to the second memory via the direct connection of the second data bus to store the received data when the memory selection logic selectively enables the second memory.