Observing embedded signals of varying clock domains by fowarding signals within a system on a chip concurrently with a logic module clock signal

摘要

Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.

主权项

1. A system on a chip (SoC) comprising:
first and second clock domains that are unequal to one another; a first node to receive a first signal, which originates within the SoC and is synchronous with the first clock domain, and output the first signal from the SoC; a second node to receive a second signal, which originates within the SoC and is asynchronous to the first clock domain and synchronous to the second clock domain, and output the first signal from the SoC; a processor core and a core clock, corresponding to the processor core and the first clock domain, to produce a core clock signal; and a logic module and a logic module clock, corresponding to the logic module and the second clock domain, to produce a logic module clock signal; wherein (a) the first and second nodes are to concurrently receive the first and second signals, (b) the first signal is not forwarded, within the SoC, concurrently with the core clock signal, and (c) the second signal is forwarded, within the SoC, concurrently with the logic module clock signal.