发明名称 Semiconductor device and method for manufacturing the same
摘要 The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.
申请公布号 US9202817(B2) 申请公布日期 2015.12.01
申请号 US201414161372 申请日期 2014.01.22
申请人 Taiwan Semiconductorr Manufacturing Co., Ltd. 发明人 Chuang Harry Hak-Lay;Wu Wei-Cheng;Kao Ya-Chen
分类号 H01L21/336;H01L27/115;H01L29/423;H01L21/28 主分类号 H01L21/336
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a dielectric layer and a dummy gate layer on a substrate; patterning the dielectric layer and the dummy gate layer to form a plurality of gate stacks on the substrate; sequentially forming a tunneling layer, a charge trapping layer, a blocking layer, and a main gate layer on the substrate; patterning the tunneling layer, the charge trapping layer, the blocking layer, and the main gate layer, such that the gate stacks become at least one split gate stack with the tunneling layer, the charge trapping layer, the blocking layer, and the main gate layer and at least one logic gate stack; forming sources and drains corresponding to the split gate stack and the logic gate stack; and respectively replacing at least one of the dummy gate layer and the main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and at least one metal logic gate.
地址 Hsinchu TW