Multi-layer semiconductor device structure

摘要

A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.

主权项

1. A method of fabricating a semiconductor device structure, the method comprising:
fabricating a first transistor layer on a substrate, the fabricating of the first transistor layer including:
patterning the substrate to define a first active region, the first active region including a first alignment structure,doping the first active region to define a conductivity type of the first transistor layer, andforming a first gate region that is coupled to the first active region, the first gate region including a second alignment structure; providing a bounding layer over the first transistor layer; patterning the bounding layer to include an opening over the first alignment structure and the second alignment structure; filling the opening of the bounding layer with a transparent or semi-transparent material; and fabricating a second transistor layer over the bounding layer, the fabricating of the second transistor layer including:
patterning the second transistor layer to define a second active region, wherein patterning the second active region includes aligning a mask layer relative to the first and the second alignment structures, and wherein the first and the second alignment structures are detectable via the opening during the patterning of the second transistor layer, andforming a second gate region that is coupled to the second active region.