Semiconductor memory device having vertical transistors

摘要

A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.

主权项

1. A device comprising:
first and second regions including first and second amplifiers, respectively; a memory cell array region formed between the first and second regions and including:
first and second conductive layers each extending in a first direction;a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element; anda plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element; a plurality of first memory cells each coupled to the other end of a corresponding one of the first elements of the first pillar elements; a plurality of second memory cells each coupled to the other end of a corresponding one of the third elements of the second pillar elements; a first interconnection connecting the other end of the second element of the first pillar elements to the first amplifier; a second interconnection connecting the other end of the fourth element of the second pillar elements to the second amplifier; and third and fourth interconnections each extending in the first direction, wherein the first pillar elements further comprises a fifth element coupled to the third interconnection at the other end thereof, and the second pillar elements further comprises a sixth element coupled to the fourth interconnection at the other end thereof.