发明名称 |
DELAY LOCKED LOOP INCLUDING A MECHANISM FOR REDUCING LOCK TIME |
摘要 |
<p>A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.</p> |
申请公布号 |
HK1169222(A1) |
申请公布日期 |
2015.11.27 |
申请号 |
HK20120109708 |
申请日期 |
2012.10.03 |
申请人 |
APPLE INC. |
发明人 |
TRIVEDI, PRADEEP R.;VON KAENEL, VINCENT R. |
分类号 |
H03L |
主分类号 |
H03L |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|