Passivation Structure of Fin Field Effect Transistor

摘要

A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material.

主权项

1. A method of fabricating a fin field effect transistor, the method comprising:
forming a first fin on a semiconductor substrate, the first fin comprising a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, the third semiconductor material having a third lattice constant, the first lattice constant being different than the second lattice constant, the second lattice constant being different than the third lattice constant; performing an oxidation process along sidewalls of the first fin; and performing a nitridation process along sidewalls of the first fin, the nitridation process forming a nitride layer along sidewalls of the first fin, the nitride layer having a first portion comprising elements of the first semiconductor material, a second portion comprising elements of the second semiconductor material, and a third portion comprising elements of the third semiconductor material.