发明名称 |
MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM |
摘要 |
An apparatus includes a device programmer and a stores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub- stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches. |
申请公布号 |
WO2015177596(A1) |
申请公布日期 |
2015.11.26 |
申请号 |
WO2014IB03267 |
申请日期 |
2014.12.12 |
申请人 |
VIA ALLIANCE SEMICONDUCTOR CO., LTD. |
发明人 |
HENRY, G., GLENN;JAIN, DINESH, K.;GASKINS, STEPHAN |
分类号 |
G11C15/04 |
主分类号 |
G11C15/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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