VIRTUAL HIERARCHICAL LAYER PROPAGATION

摘要

Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

主权项

1. A computer-implemented method for design analysis comprising:
identifying a cell and multiple instances of the cell within a semiconductor design that includes a plurality of cells and a plurality of hierarchical design levels where the cell and the multiple instances of the cell comprise the plurality of cells; generating virtual hierarchical layer (VHL) shapes, based on polygons which overlap the cell, in response to an algorithm operation; and propagating the VHL shapes to a subsequent algorithm operation.