| 摘要 |
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation. |
| 主权项 |
1. A substrate comprising:
a test data in lead; a test clock lead; a test reset lead; a test mode select lead; a command input lead; a command control lead; a match lead; an address input lead; an address command lead; state machine circuitry having a test data input coupled with the test data in lead, a test clock input coupled with the test clock lead, a test reset input coupled with the test reset lead, an enable input, a reset input, a command output coupled with the command input lead, a command control output coupled with the command input lead, a match input coupled with the match lead, an address output coupled with the address input lead, and an address control output coupled with the address control lead; and TAP state monitor circuitry having a test mode select input coupled with the test mode select lead, a test clock input coupled with the test clock lead, a test reset input coupled with the test reset lead, an enable output coupled with the enable input, and a reset output coupled with the reset input. |
