发明名称 |
GALLIUM NITRIDE FIELD EFFECT TRANSISTOR WITH BURIED FIELD PLATE PROTECTED LATERAL CHANNEL |
摘要 |
A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer. |
申请公布号 |
US2015340449(A1) |
申请公布日期 |
2015.11.26 |
申请号 |
US201514813661 |
申请日期 |
2015.07.30 |
申请人 |
AVOGY, INC. |
发明人 |
Aktas Ozgur;Kizilyalli Isik C. |
分类号 |
H01L29/40;H01L29/20;H01L29/10;H01L29/78 |
主分类号 |
H01L29/40 |
代理机构 |
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代理人 |
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主权项 |
1. A lateral-drift GaN field-effect transistor (FET), comprising:
a substrate; a first GaN layer coupled to the substrate, wherein the first GaN layer has a first conductivity type; a second GaN layer coupled to the first GaN layer, wherein the second GaN layer has a second conductivity type and comprises a void exposing a portion of the first GaN layer; a third GaN layer coupled to the second GaN layer and to the exposed portion of the first GaN layer, wherein the third GaN layer has a third conductivity type and comprises a void exposing a portion of the second GaN layer; a source structure coupled to the third GaN layer, wherein a first portion of the third GaN layer is disposed between the source structure and the second GaN layer; a drain structure coupled to the third GaN layer; and a gate structure coupled to the third GaN layer, wherein a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer. |
地址 |
San Jose CA US |