| 摘要 |
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified. |
| 主权项 |
1. An integrated circuit comprising a solid state memory, the memory comprising:
an array of solid-state memory cells arranged in rows and columns, each row of the memory cells connected to a word line, each column of the memory cells connected to a bit line, each memory cell comprising:
a first inverter, comprising:
a first load; anda first n-channel driver transistor having a gate, and having a source/drain path connected to the first load at a first storage node, the first load and the source/drain path of the first driver transistor connected in series between an array power supply node and a first array ground node;a second inverter, comprising:
a second load; anda second n-channel driver transistor having a gate connected to the first storage node, and having a source/drain path connected to the second load at a second storage node, the second storage node being connected to the gate of the first driver transistor, the second load and the source/drain path of the second driver transistor connected in series between the array power supply node and a second array ground node; and a first pass transistor having a source/drain path connected between the first storage node and a first bit line associated with a column of memory cells containing the memory cell, and having a gate connected to a word line associated with a row of memory cells containing the memory cell; a power supply conductor extending over the array and connected to the array power supply node of each of a first plurality of memory cells; a first ground conductor extending over the array and connected to the first array ground node of each of the first plurality of memory cells; a second ground conductor extending over the array and connected to the second array ground node of each of the first plurality of memory cells; and peripheral circuitry, coupled to the word lines and bit lines, for selecting one or more cells in the array for access. |
