| 摘要 |
DC-DC converter PWM controllers and dual counter digital integrators are presented for integrating an error between a reference voltage signal and a feedback voltage signal, in which a comparator, dual counters, and a DAC are used to provide a compensated reference to a modulator loop comparator which generates a PWM switching signal for controlling a power converter output voltage, with the second counter being selectively incremented or decremented when the first counter output indicates a predetermined value after the first counter output transitions in one direction through a predetermined count range to enhance loop stability, and a startup mode control allows fast integrator operation during initialization, with the ability to freeze integrator operation during overcurrent conditions. |
| 主权项 |
1. A DC to DC converter, comprising:
a switching circuit comprising at least one switch connected to a switching node; a modulator circuit providing a switching control signal to selectively actuate and deactuate the at least one switch to control an output voltage of a converter output node; a feedback circuit coupled with the converter output node to provide a feedback voltage signal based at least partially on the output voltage; a loop comparator circuit with a first comparator input connected to receive the feedback voltage signal, a second comparator input connected to receive a compensated reference signal, and a loop comparator output providing a loop comparator output signal to the modulator circuit to regulate the output voltage based on the feedback voltage signal and the compensated reference signal; a digital integrator circuit, comprising:
a reference circuit providing an integrator reference voltage signal based at least partially on a reference voltage,a comparator circuit comprising a first input coupled with the reference circuit to receive the integrator reference voltage signal, a second input coupled with the feedback circuit to receive the feedback voltage signal, and a comparator output providing a binary comparator output signal indicating whether the reference voltage signal is greater than the feedback voltage signal, anda dual counter circuit, comprising:
a multi-bit first counter comprising a first clock input coupled with an integrator circuit clock source, a first up/down count input coupled to receive the comparator output signal from the comparator circuit, and a plurality of first counter bit outputs providing signals indicating a multi-bit first counter output value,a multi-bit second counter comprising a second clock input, a second up/down count input, and a plurality of second counter bit outputs providing signals indicating a multi-bit second counter output value, anda logic circuit operative to initially increment or decrement the second counter responsive to the first counter bit outputs initially indicating a predetermined value of the first counter, and thereafter increment or decrement the second counter responsive to the first counter bit outputs again indicating the predetermined value after the first counter bit outputs transition in one direction through a full value range of the first counter; and a digital to analog converter with a plurality of inputs connected to the second counter bit outputs, and an output controlling the compensated reference signal provided to the second comparator input based at least partially on the second counter bit outputs and the reference voltage. |
