| 摘要 |
<p>A processor comprises: an instruction fetch unit to fetch a double-multiplication instruction from a memory subsystem, the double multiplication instruction having three source operand values; a decode unit 830 to decode the double multiplication instruction to generate at least one uop; and an execution unit 841 to execute the uop a first time to multiply a first and a second of the three source operand values to generate a first intermediate result and to execute the uop a second time to multiply the intermediate result with a third of the three source operand values to generate a final result. The execution unit may comprise a delay buffer 905 to delay the uop prior to executing the uop a second time, and may further comprise a reservation station 902 to schedule the double-multiply instruction for execution by at least one functional unit 912, which may be a fused multiply and add functional unit 910. The source operands may be floating point values. The double-multiplication instruction may include an immediate value to indicate a sign for each of the operands, and this may be a three-bit value.</p> |
