发明名称 Semiconductor package and method of fabricating the same
摘要 Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.
申请公布号 US9196538(B2) 申请公布日期 2015.11.24
申请号 US201313950292 申请日期 2013.07.25
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Hong Min gi
分类号 H01L21/00;H01L21/82;H01L21/56;H01L23/00;H01L23/31 主分类号 H01L21/00
代理机构 Muir Patent Law, PLLC 代理人 Muir Patent Law, PLLC
主权项 1. A method of fabricating a semiconductor package, the method comprising: preparing a wiring board including at least a first mounting region and a first molding region surrounding the first mounting region; forming a sacrificial layer having a third surface and a fourth surface opposite the third surface, on a first surface of the wiring board by adhering the third surface to the first surface; forming at least a first through-hole, the first through-hole passing through the wiring board at the mounting region and passing through the sacrificial layer; mounting at least one semiconductor chip on a second surface of the wiring board opposite the first surface, the at least one semiconductor chip mounted in the mounting region and physically and electrically connected to the wiring board using a plurality of interconnection terminals; forming a molding, the molding covering the at least one semiconductor chip, filling in a space between the wiring board and the at least one semiconductor chip not filled in by the interconnection terminals, filling at least the first through-hole, and forming a portion of the molding below the first surface of the wiring board and that contacts the sacrificial layer; and removing the sacrificial layer and the portion of the molding below the first surface of the wiring board, wherein the sacrificial layer is an adhesive.
地址 Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do KR