| 摘要 |
PROBLEM TO BE SOLVED: To provide a matrix operation circuit configured to reduce the circuit scale when matrix operation is implemented by means of hardware.SOLUTION: A matrix operation circuit includes one-dimensional LUT addition circuits arranged in a matrix with m rows and n columns. Each of the one-dimensional LUT addition circuits includes: an LUT which stores a result of binary operation of an element avh of a matrix corresponding to the position of the circuit and a value of an element of an input vector X, in association with a value of the element of the input vector X; and an addition circuit which reads the binary operation result corresponding to a value of an element in a row in the input vector X where the circuit is located, and outputs a result of adding an output of the one-dimensional LUT addition circuit located in the next column in the same row as the circuit and the read binary operation result, to a one-dimensional LUT addition circuit located in the previous column in the same row as the circuit. Before matrix operation, the LUT stores results of binary operation of the element avh corresponding to the position of each of the one-dimensional LUT addition circuits and an element of the input vector X. |
