| 发明名称 |
Semiconductor test device |
| 摘要 |
A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit. |
| 申请公布号 |
US9196382(B2) |
申请公布日期 |
2015.11.24 |
| 申请号 |
US201414253598 |
申请日期 |
2014.04.15 |
| 申请人 |
SK HYNIX INC. |
发明人 |
Lee Wan Seob |
| 分类号 |
G11C29/00;G11C29/12;G11C29/36 |
主分类号 |
G11C29/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor test device comprising:
a clock generator suitable for generating an internal clock signal in response to a test mode signal during a test mode; a data generator suitable for generating internal data in response to the internal clock signal; and a data latch circuit suitable for latching the internal data in response to the internal clock signal, and outputting a rising clock synchronized with a rising edge of the internal clock signal, a falling clock synchronized with a falling edge of the internal clock signal, and the latched data to an internal logic circuit, wherein the data latch circuit latches the internal data in response to a rising edge of the rising clock and a rising edge of the falling clock. |
| 地址 |
Icheon KR |
