发明名称 |
Semiconductor device |
摘要 |
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area. |
申请公布号 |
US9196626(B2) |
申请公布日期 |
2015.11.24 |
申请号 |
US201414272853 |
申请日期 |
2014.05.08 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Kato Kiyoshi;Onuki Tatsuya |
分类号 |
H01L29/10;H01L29/12;H01L27/115;H01L27/108;G11C11/00;H01L27/105;H01L27/11 |
主分类号 |
H01L29/10 |
代理机构 |
Fish & Richardson P.C. |
代理人 |
Fish & Richardson P.C. |
主权项 |
1. A semiconductor device comprising:
a plurality of memories, each of the plurality of memories comprising:
a volatile memory including a first data holding portion; anda nonvolatile memory including a second data holding portion,wherein:the second data holding portion includes a first transistor and a first capacitor,a first electrode of the first transistor is electrically connected to the first data holding portion,a second electrode of the first transistor is electrically connected to a first electrode of the first capacitor,the first electrode of the first capacitor and the first electrode of the first transistor are on a same layer, anda second electrode of the first capacitor and a gate of the first transistor are on a same layer; and a first wiring between the plurality of memories,
wherein:the first wiring is configured to electrically connect gates of first transistors of the plurality of memories, anda layer in which the first wiring is provided and a layer in which the gate of the first transistor is provided are different. |
地址 |
Kanagawa-ken JP |