| 摘要 |
PROBLEM TO BE SOLVED: To prevent metastability from being generated between asynchronous clock regions by suppressing increase of latency during data transfer between the asynchronous clock regions.SOLUTION: On the basis of a cycle difference between a first cycle of a first clock to latch data at a first edge in a circuit 10 and a second cycle of a second clock to latch data at a second edge in a second circuit 20, a clock phase determination section 30 determines whether a time difference between the first edge and the second edge after predetermined cycles is greater than a setup time and a hold time of an input section. If it is determined that the time difference between the first edge and the second edge after the predetermined cycles is greater than the setup time and the hold time, a control signal is outputted to the second circuit 20 by the clock phase determination circuit 30 in such a manner that the input section latches the data after the predetermined cycles and if determined smaller, a control signal for inhibiting the input section from latching the data after the predetermined cycles is outputted to the second circuit 20. |
