Electrostatic discharge clamping devices with tracing circuitry

摘要

Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

主权项

1. An electrostatic discharge (ESD) protection circuit arrangement comprising:
at least one MOS buffer transistor configured to receive an input signal from a first functional circuit block at a gate of the at least one MOS buffer transistor and to provide a first portion of an output signal to a second functional circuit block; a leakage current prevention circuit comprising: at least one MOS clamping transistor coupled to the at least one MOS buffer transistor; and at least one MOS tracing circuitry coupled to the at least one MOS clamping transistor, the at least one MOS tracing circuitry having at least one MOS tracing transistor configured to control a voltage at a gate of the at least one MOS clamping transistor; wherein at least one of a source or a drain of the at least one MOS clamping transistor or the at least one MOS tracing transistor is coupled to a first supply voltage, and wherein the at least one MOS tracing transistor of a first MOS tracing circuitry comprises a first MOS tracing transistor and a second MOS tracing transistor coupled to the first MOS tracing transistor, and wherein the first MOS tracing transistor and the second MOS tracing transistor being transistors of a first MOS type.