发明名称 |
Low sensing current non-volatile flip-flop |
摘要 |
A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage. |
申请公布号 |
US9196337(B2) |
申请公布日期 |
2015.11.24 |
申请号 |
US201213613205 |
申请日期 |
2012.09.13 |
申请人 |
QUALCOMM Incorporated;Industry-Academic Cooperation Foundation, Yonsei University |
发明人 |
Jung Seong-Ook;Jung Youngdon;Ryu Kyungho;Kim Jisu;Kim Jung Pill;Kang Seung H. |
分类号 |
G11C11/16;G11C7/06;G11C14/00 |
主分类号 |
G11C11/16 |
代理机构 |
|
代理人 |
Wong Chui-kiu Teresa;Holdaway Paul |
主权项 |
1. A magnetic tunnel junction (MTJ) flip flop apparatus, comprising a first stage including a first MTJ and a second MTJ coupled to the first MTJ, the first stage including a first low current sense path from a first precharge node through the first MT; and a second low current sense path from a second precharge node through the second MTJ; and
a second stage separate from the first stage, the second stage including a third current sense path from a supply voltage node to a ground node via a first second stage transistor and a fourth current sense path from the supply voltage to the ground node via a second second stage transistor, in which the third current sense path excludes the first precharge node and the fourth current sense path excludes the second precharge node; and wherein the first second stage transistor includes a first second stage transistor gate coupled to the second precharge node, and the second second stage transistor includes a second second stage transistor gate coupled to the first precharge node. |
地址 |
San Diego CA US |