Cycle modulation circuit for limiting peak voltage and associated power supply

摘要

A cycle modulation circuit for limiting voltage peak value of a power supply employed an active clamp. The power supply receives an input power which is modulated through a power driving unit to become a driving power transformed through a transformer to be output. The cycle modulation circuit includes a comparison unit and a linear voltage generation unit. The comparison unit receives the input power to generate a level signal which is used as a base value to compare level with an oscillation signal generated by the linear voltage generation unit, thereby to modulate and output a pulse width limit signal with a composite cycle consisting of a high level and a low level. The pulse width limit signal is input to the power driving unit to limit the peak value of the driving power modulated by the power driving unit.

主权项

1. A power supply, comprising:
a cycle modulation circuit; and a power driving unit, wherein the cycle modulation circuit is to limit voltage peak value for the power supply employing an active clamp, the power driving unit includes a pulse width modulation (PWM) circuit to generate a PWM signal, the power driving unit is connected to an input voltage source to receive an input power and modulate the input power to become a driving power according to the PWM signal and send the driving power to a primary side winding of a transformer of the power supply, and the cycle modulation circuit comprises:
a comparison unit which has two signal input ends and a signal output end to output a pulse width limit signal, one of the signal input ends being electrically connected to the input voltage source to receive a level signal representing a voltage value of the input power; anda linear voltage generation unit to generate an oscillation signal of a linear voltage value, and the oscillation signal is sent to another signal input end of the comparison unit;wherein the comparison unit treats the level signal as a base value to compare level with the oscillation signal to modulate and output the pulse width limit signal with a composite cycle consisting of a high level and a low level, the pulse width limit signal being sent to the power driving unit at a rear end so that the PWM circuit thereof determines an allowable duty cycle within a limited voltage peak value range provided by the pulse width limit signal to limit the peak value of the driving power.