Method and apparatus for integrated circuit mask patterning

摘要

Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

主权项

1. A method, comprising:
receiving a design layout of an integrated circuit (IC), the design layout having a first main feature and a second main feature; and adding an assist feature to the design layout, the assist feature satisfying mask creation rules when the assist feature is added, wherein:
the assist feature has a first length and a first width;the assist feature connects the first main feature and the second main feature by the first length and is oriented orthogonally to at least one of the first and second main features; andthe first width is sub-resolution in a photolithography process; performing an optical proximity correction (OPC) process to the first and second main features to optimize the design layout; and performing a mask rule checking (MRC) process to the optimized design layout, after performing the OPC process.