| 发明名称 | Word line coupling prevention using 3D integrated circuit | ||
| 摘要 | A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to the first line. The word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line. | ||
| 申请公布号 | US9196582(B2) | 申请公布日期 | 2015.11.24 |
| 申请号 | US201314087016 | 申请日期 | 2013.11.22 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Hsu Kuoyuan (Peter) |
| 分类号 | H01L23/522;H01L21/768 | 主分类号 | H01L23/522 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A memory comprising: a first layer on a first level, the first layer comprising a first line; a second layer on a second level different from the first level, the second layer comprising: a series of bit-cells;a word line driver; anda word line coupled to the word line driver; and a first plurality of through vias coupling the word line to the first line, wherein the word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line. | ||
| 地址 | TW | ||