Scanning signal line drive circuit and display device equipped with same

摘要

This liquid crystal display device allows outputs from RS-FF circuits (401 to 409) and switch circuits (411 to 419), which function as a shift register, to be provided as scanning signals that are selectively activated during odd and even scanning line selection periods, by simply changing the potential of an enable signal (EN) (i.e., by simply providing an EN signal line), which achieves interlacing drive that allows a reduction in the number of polarity inversions, thereby making it possible to reduce power consumption and a wiring area for control lines and achieve simple control which allows circuit simplification, resulting in a reduced frame area and a display panel which is compact as a whole.

主权项

1. A scanning signal line drive circuit for performing interlaced scanning to drive a plurality of scanning signal lines provided in an active-matrix display device such that odd scanning signal lines are sequentially driven by a corresponding scanning signals during a first period, and even scanning signal lines are sequentially driven by a corresponding scanning signals during a second period, the circuit comprising:
a shift register for providing output signals from output terminals coupled to their corresponding scanning signal lines, the output signals being activated sequentially; and a selection circuit for transmitting the output signals such that output signals from odd output terminals are provided only to their corresponding odd scanning signal lines during the first period, and output signals from even output terminals are provided only to their corresponding even scanning signal lines during the second period, wherein, the shift register provides first and second output signals during the first period and also provides third and fourth output signals during the second period, the first output signals being outputted from the odd output terminals and having active periods which are equivalent to active periods of scanning signals corresponding to the odd output terminals, the second output signals being outputted from the even output terminals and having active periods which correspond to invalid periods of the scanning signals and have a length less than or equal to the invalid period, the third output signals being outputted from the even output terminals and having active periods which are equivalent to active periods of scanning signals corresponding the output terminals, the fourth output signals being outputted from the odd output terminals and having active periods which correspond to invalid periods of the scanning signals and have a length less than or equal to the invalid period.