发明名称 |
Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same |
摘要 |
A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals. |
申请公布号 |
US9197202(B2) |
申请公布日期 |
2015.11.24 |
申请号 |
US201314092251 |
申请日期 |
2013.11.27 |
申请人 |
SK Hynix Inc. |
发明人 |
Jang Jae Min;Kim Yong Ju;Kwon Dae Han;Cha Kil Ho |
分类号 |
H03H11/16;H03K3/00;H03K5/13 |
主分类号 |
H03H11/16 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A phase mixing circuit comprising:
a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; an inverting input unit configured to receive the first and second clocks, and generate an inverted signal of the first clock and an inverted signal of the second clock; a second mixing unit configured to mix phases of the inverted signal of the first clock and the inverted signal of the second clock at the predetermined ratio; an inverting driving section configured to receive output of the second mixing unit, and generate a second mixed signal; a delay unit configured to delay the first mixed signal, wherein a delay amount of the delay unit corresponds to delay amount of the inverting input unit and the inverting driving section; and an output unit configured to generate an output signal based on outputs of the delay unit and the inverting driving section. |
地址 |
Gyeonggi-do KR |