Multiple sector parallel access memory array with error correction

摘要

The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.

主权项

1. A method for accessing a memory array comprising:
grouping bits for error correction such that (i) bits obtained by accessing a multiple bit-per-cell memory element having at least two bits at a row address and a column address are divided across two groupings and (ii) fewer bits from the multiple bit-per-cell memory element are included in any grouping able to be corrected using an error-correcting algorithm; receiving a data-access request to access a first bit in the multiple bit-per-cell memory element, the first bit belonging to a first grouping; accessing all of the bits in the multiple bit-per-cell memory element, wherein a second bit in the multiple bit-per-cell memory element belongs to a second grouping different from the first grouping; and storing the first and second bits in at least one buffers, thereby avoiding having to re-access the row address and column address at a later point in time to access the second bits.