Stress release layout and associated methods and devices

摘要

An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

主权项

1. A semiconductor device, comprising:
a semiconductor substrate; a pixel array disposed within the semiconductor substrate; one or more metal stress release features on the semiconductor substrate and arranged around a periphery of the pixel array, the one or more stress release features comprising at least one continuous strip parallel to a side of the pixel array; and an interlayer dielectric layer over the pixel array and the one or more metal stress release features, the interlayer dielectric layer being a lowermost interlayer dielectric layer.