发明名称 Method for manufacturing semiconductor device
摘要 A method for manufacturing a semiconductor device includes: forming a metal layer on a semiconductor layer; forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer, the pattern corresponding to the pattern of the gate bus line having a deficient part; forming a mask layer which covers the metal layer exposed in the deficient part; and patterning the metal layer by using the plated layer and the mask layer as a mask.
申请公布号 US9196492(B2) 申请公布日期 2015.11.24
申请号 US201213661471 申请日期 2012.10.26
申请人 SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC. 发明人 Kajii Kiyoshi
分类号 H01L21/28;H01L27/02;H01L29/66;H01L29/778;H01L29/20 主分类号 H01L21/28
代理机构 Westerman, Hattori, Daniels & Adrian, LLP 代理人 Westerman, Hattori, Daniels & Adrian, LLP
主权项 1. A method for manufacturing a semiconductor device having a gate bus line which couples gate fingers of a plurality of FETs and gate pads comprising: forming a metal layer on a semiconductor layer; forming a first mask layer on the metal layer, the first mask layer not covering a first pattern for a first portion the gate bus line; forming a plated layer within the first pattern for the first portion of the gate bus line on the metal layer with use of the first mask layer as a mask; forming a second mask layer which covers a second pattern for a second portion of the gate bus line on the metal layer while exposing the plated layer, the second mask layer having a width, in a first direction orthogonal to a second direction in which the gate bus line extends, smaller than a width in the first direction of the plated layer formed within the first pattern for the first portion of the gate bus line, the second portion of the gate bus line being connected to the first portion of the gate bus line in the second direction; and etching the metal layer with use of the plated layer and the second mask layer as a mask so that the metal layer beneath the second mask layer becomes the second portion of the gate bus line, the second portion of the gate bus line having a smaller width in the first direction than the first portion of the gate bus line, wherein the second portion of the gate bus line is located between the gate pads.
地址 Yokohama-shi JP