发明名称 容量性負荷駆動回路
摘要 <p>A driving circuit 1A is a circuit selectively outputting one of a staircase wave and a square wave from an output terminal 11, to drive a capacitive load 52, and includes a high-voltage power source 41 supplying a constant voltage VH, an FET 21 connected in series between the output terminal 11 and the high-voltage power source 41, a transformer 22 in which an output side coil is connected to a gate of the FET 21, an input terminal 12a connected to an input side coil of the transformer 22 via a capacitive element 23, a high-voltage power source 42 supplying a constant voltage VL lower than the constant voltage VH, an FET 31 connected in series between the output terminal 11 and the high-voltage power source 42, a transformer 32 in which an output side coil is connected to a gate of the FET 31, and an input terminal 12b connected to an input side coil of the transformer 32 via a capacitive element 33. Thereby, the circuit is realized which is capable of suitably providing a stair-shaped high-voltage pulse to the capacitive load.</p>
申请公布号 JP5820241(B2) 申请公布日期 2015.11.24
申请号 JP20110241337 申请日期 2011.11.02
申请人 发明人
分类号 H03K4/02;G02F1/03;H01S3/107 主分类号 H03K4/02
代理机构 代理人
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