Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

摘要

Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

主权项

1. A method of memory operation in a multi-bank, multi-pipe SRAM device, the method comprising:
executing a read operation and a write operation sequentially in a fixed unit of time spanning two cycles of the SRAM device operation, the SRAM device comprising a memory array including a plurality of ‘T’ SRAM banks and a set of two separate and distinct pipes associated with each of the SRAM banks, each set of pipes including a write pipe and a read pipe; as sequential read operations are initiated, propagating (i) read address values from input pins to the memory array and (ii) read data values from the memory array to output pins in an alternating manner between 2 read pipes; and as sequential write operations are initiated, propagating (i) write address values and write data values from input pins to the memory array in an alternating manner between 2 write pipes; wherein each read/write pair of operations are executed in the memory array within a fixed unit of time, independent of cycle time; and wherein, as a function of executing the read/write operations sequentially in a fixed unit of time that spans 2 cycles as compared to spanning one cycle in single-pipe operation, a maximum operating frequency of the SRAM device is multiplied by two as compared to a single-pipe SRAM configuration.