TRANSISTORS WITH ISOLATION REGIONS

摘要

A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

主权项

1. A method of forming a transistor device, comprising:
forming a source, a gate, and a drain on a III-N semiconductor material, the III-N semiconductor material having a channel therein, the III-N semiconductor material including a gate region between the source and the drain and a plurality of channel access regions between the source and the gate and between the drain and the gate, respectively; and forming a plurality of isolation regions in the III-N semiconductor material, the plurality of isolation regions serving to improve the efficiency of hole collection from the III-N semiconductor material; wherein the plurality of isolation regions are in the gate region and serve to reduce an effective width of the channel in the gate region without substantially reducing the effective width of the channel in the channel access regions.