FOUR-STAGE CIRCUIT ARCHITECTURE FOR DETECTING PULSED SIGNALS

摘要

An electrical circuit includes a sensor configured to generate a current signal comprising a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from sources other than the target source, a trans-impedance amplifier that amplifies the current signal and generate a low noise signal, and a high pass filter that converts the low noise signal into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive and negative amplitudes. The circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The circuit further includes at least one analog-to-digital converter that receives the integrated values.

主权项

1. An electrical circuit, comprising:
a sensor configured to generate a current signal, the current signal comprising at least a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from one or more sources other than the target source; a first stage comprising a trans-impedance amplifier configured to amplify the current signal and generate a low noise signal; a second stage comprising a high pass filter configured to convert the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude; a third stage comprising:
a positive integrating amplifier configured to receive the positive amplitude of the AC signal and generate a positive integrated value over an integration period, anda negative integrating amplifier configured to receive the negative amplitude of the AC signal and generate a negative integrated value over the integration period; and a fourth stage comprising at least an analog-to-digital converter (ADC) configured to receive the positive and negative integrated values and generate a digital value indicative of the first portion of the current signal based on the positive and negative integrated values.