发明名称 |
METHOD FOR AUTOMATICALLY GENERATING A NETLIST OF AN FPGA PROGRAM |
摘要 |
A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build. |
申请公布号 |
US2015331983(A1) |
申请公布日期 |
2015.11.19 |
申请号 |
US201514711116 |
申请日期 |
2015.05.13 |
申请人 |
dSPACE digital signal processing and control engineering GmbH |
发明人 |
KALTE Heiko;LUBELEY Dominik |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method for generating a netlist of an FPGA program, an underlying model of the FPGA program being composed of at least two components, the method comprising:
assigning each component a separate partition on the FPGA; performing an independent build of a netlist for each component; generating an overall classification from the netlists of the components; and automatically starting the build jobs after a trigger event, the trigger event being a saving of a component, the exiting of a component of the model, or a time-controlled, automated initiation of a build. |
地址 |
Paderborn DE |