DUAL SILICIDE FORMATION METHOD TO EMBED SPLIT GATE FLASH MEMORY IN HIGH-K METAL GATE (HKMG) TECHNOLOGY

摘要

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

主权项

1. An integrated circuit (IC) comprising:
a semiconductor substrate including a periphery region and a memory cell region; a high-k metal gate (HKMG) gate electrode disposed on the periphery region; a first memory cell disposed on the memory cell region, comprising a select gate (SG) and a memory gate (MG); a silicide layer disposed on a SG top surface or a MG top surface of the first memory cell; a hard mask layer in contact with an upper surface of the HKMG gate electrode; and metal contacts extending into the silicide layer on the SG top surface or the MG top surface.