INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE

摘要

A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.

主权项

1. A circuit structure comprising:
a substrate having formed thereon:
a first transistor having a source, a drain, and a channel;a second transistor having a source, a drain, and a channel, and being of a complimentary type to said first transistor; a first full metal gate stack formed over said channel of said first transistor; a second full metal gate stack formed over said channel of said second transistor; a first encapsulation enclosing said first full metal gate stack; a second encapsulation enclosing said second full metal gate stack; a silicided contact between said first and second encapsulations; and a self-aligned contact projecting from said silicided contact; wherein said first full metal gate stack is formed of material which tunes said first transistor to a first threshold voltage and said second full metal gate stack is formed of material which tunes said second transistor to a second threshold voltage different than said first threshold voltage.