发明名称 半導体装置およびその製造方法
摘要 An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.
申请公布号 JP5816560(B2) 申请公布日期 2015.11.18
申请号 JP20120002234 申请日期 2012.01.10
申请人 发明人
分类号 H01L21/8234;H01L21/336;H01L21/8238;H01L27/088;H01L27/092;H01L29/78;H01L29/786 主分类号 H01L21/8234
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