发明名称 VERTICAL SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To achieve stable vertical deflection by discriminating between a normal synchronizing signal and a noise by discriminating the ratio of a horizontal frequency to a vertical frequency, and obtaining a synchronizing signal by resetting a frequency dividing circuit only when the synchronizing signal is normal. CONSTITUTION:A TV signal from a terminal X is separated synchronously, and the resulting signal is integrated by a circuit 3 to obtain a vertical synchronizing signal A, which is detected by using a threshold level K to obtain a pulse B. A clock pulse from a terminal Y has a frequency 2fH and a frequency dividing circuit 6 includes a circuit which, if once reset, counts 525 pulses thereafter and then reset by itself; a vertical pulse obtained by the circuit drives a vertical deflecting circuit 8 through a driving circuit 7. A detecting circuit 9, on the other hand, discriminates the ratio of a horizontal to a vertical frequency to discriminate between a normal synchronizing signal and a noise, and only when it is normal, a reset control circuit 5 applies a reset signal to the frequency dividing circuit 6. Thus, the stability of vertical synchronism is improved to eliminate the disorder of deflection.
申请公布号 JPS57155882(A) 申请公布日期 1982.09.27
申请号 JP19810040947 申请日期 1981.03.20
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SATOU SUKEYUKI;YAMAGUCHI NAKAO;SHIOTANI YUUICHI
分类号 H04N5/06;H04N5/08 主分类号 H04N5/06
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