Double data rate counter, and analog-digital converting apparatus and CMOS image sensor using the same

摘要

A double data rate (DDR) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (LSB) of the DDR counter, a determination unit suitable for generating the control signal based on the last bit state of the LSB in a reset counting period, and a second latch stage suitable for receiving the LSB as a clock input to generate a higher bit of the LSB at least in a main counting period.

主权项

1. A double data rate (DDR) counter comprising:
a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock; a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (LSB) of the DDR counter; a determination unit suitable for generating the control signal based on the last bit state of the LSB in a reset counting period; and a second latch stage suitable for receiving the LSB as a clock input to generate a higher bit of the LSB at least in a main counting period.