Fluctuation resistant FDSOI transistor with implanted subchannel

摘要

The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.

主权项

1. A method of forming a MOSFET comprising:
providing an underlying substrate with a buried oxide layer thereon and a first semiconductor layer on the buried oxide layer; forming a sacrificial gate structure above a region designated to be the transistor channel; creating source and drain structures in the first semiconductor layer comprising source and drain extensions, sidewall spacers adjacent the sacrificial gate, and highly conductive source and drain regions contacting the source and drain extensions, respectively; etching away the sacrificial gate structure; implanting in the first semiconductor layer aligned with and below the sidewall spacers, a doped region adjacent and extending to the buried oxide layer, that comprises forming the doped region by ion implantation using the sidewall spacers as a mask, and etching away part of the first semiconductor layer by an anisotropic process using the gate spacers as a mask; epitaxially growing a semiconductor channel region in a recess in the first semiconductor layer over the doped region of a first doping level that extends to the buried oxide layer, the recess being formed by anisotropic processes using the gate spacers as a mask; depositing a dielectric stack over the epitaxially grown semiconductor channel region; and, depositing a conductive gate over the dielectric stack; wherein epitaxially growing a semiconductor channel region in the recess and all subsequent processes are low temperature processes not subjecting the MOSFET to temperatures exceeding 650° C.