| 发明名称 | Chip level critical point analysis with manufacturer specific data | ||
| 摘要 | A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path. | ||
| 申请公布号 | US9189587(B2) | 申请公布日期 | 2015.11.17 |
| 申请号 | US201314045242 | 申请日期 | 2013.10.03 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Shih I-Chang;Lo Jen-Chieh;Lin Tzu-Chin;Wu Ping-Chieh;Cheng Ying-Chou;Lai Chih-Ming;Liu Ru-Gun |
| 分类号 | G06F17/50 | 主分类号 | G06F17/50 |
| 代理机构 | Haynes and Boone, LLP | 代理人 | Haynes and Boone, LLP |
| 主权项 | 1. A method performed by a computer processing system, the method comprising: analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers, the critical points being based at least in part on manufacturer specific process parameters; assigning a critical point value to each of the critical points, wherein the critical point value is weighted based on a distance from the critical point to a common point in the integrated circuit design; analyzing a path through the integrated circuit design across multiple integrated circuit design layers; and determining a sum of critical point values of each critical point along the path. | ||
| 地址 | Hsin-Chu TW | ||