Clock generation circuit and semiconductor memory device employing the same

摘要

A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.

主权项

1. A semiconductor memory device, comprising:
a first internal clock generation circuit configured to generate a first internal clock signal by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device; a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal; a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage; a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal; and a data output circuit configured to output a data in synchronization with the synchronization clock signal.