Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance

摘要

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

主权项

1. A method for fabricating an integrated circuit, comprising:
forming a sacrificial gate structure over a semiconductor substrate, wherein a top surface of the sacrificial gate structure is located a first distance from the semiconductor substrate; forming a spacer around the sacrificial gate structure; depositing a dielectric material over the spacer and the semiconductor substrate; selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material, wherein the trench is bounded by a trench surface, wherein a top end of the trench surface is located a second distance from the semiconductor substrate, and wherein the second distance is greater than the first distance; and depositing a replacement spacer material along the trench surface and merging an upper region of the replacement spacer material to form a merged upper region of the replacement spacer material, to enclose a void within the replacement spacer material and to partially enclose a pocket within the replacement spacer material, wherein the void is formed around at least one sidewall of the sacrificial gate structure, the pocket is formed directly over and overlaps the sacrificial gate structure, and the pocket does not overlap the void.